The invention generally relates to digital circuits, and more particularly relates to a clock buffer circuit having a short propagation delay.
Along with the fulfillment of the promised performance and functionality of a Very Large Scale Integration (VLSI) digital integrated circuit chip, come new challenges. At the very heart of all synchronous digital systems are clock pulses. To maintain synchronization of numerous functional blocks fabricated at various locations on the VLSI chip, the clock pulses must be redistributed to each such functional block. To reduce clock loading and to increase clock driving strength, a number of clock buffer circuits are used.
Various clock buffer circuits are known in the prior art. FIG. 1A is a functional block diagram of a typical clock buffer circuit using a string of inverting amplifiers. FIG. 1B is an example schematic diagram for the circuit of FIG. 1A, showing an implementation using type n Field Effect transistors (nFETs) and type p Field Effect Transistors (pFETs).
While the clock buffer circuits of the prior art provide some advantages, some limitations still remain. Simulation predicts that for the prior art circuit in FIG. 1B, a propagation delay along an electrical path through the circuit from an input, clock_in, to an output, clock_out, is substantially longer than approximately one hundred and thirty picoseconds (when the circuit is fabricated using a 0.18 micron process and voltage swing of approximately one and a third volt are used.)
Such a long propagation delay through the clock buffer circuit of the prior art leads to other difficulties, such as increased power dissipation, as well as increased accumulated clock timing skew at the various locations on the VLSI chip due to processing, voltage and temperature variations.
What is needed is a clock buffer circuit having a reduced propagation delay therethrough relative to such prior art, so as to provide reduced accumulated clock timing skew and reduced power dissipation.
The invention provides a novel clock buffer circuit having a reduced propagation delay therethrough relative to the prior art discussed previously herein, so as to provide reduced accumulated clock timing skew and reduced power dissipation.
Briefly, and in general terms the clock buffer circuit of the invention has a clock input for receiving an initial clock pulse thereto, and a clock output for transmitting a buffered clock pulse therethrough. A first driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from a low voltage level to a high voltage level. A second driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from the high voltage level to the low voltage level.
The clock buffer circuit further includes a holder circuit coupled with the first and second driver chain and with the clock output for alternately holding the clock output at one of the high and low voltage levels. A trigger circuit for the first driver chain is coupled with the clock input for generating a first level trigger pulse in response thereto, and also is coupled with the first driver chain for applying the first level trigger pulse thereto. Similarly, a trigger circuit for the second driver chain is coupled with the clock input for generating a trigger pulse in response thereto, and also is coupled with the second driver chain for applying the trigger pulse thereto.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.